"We wanted to design the best-in-class performance microprocessor and DSP cores for our specific type of application. Our aggressive schedules required us to perform simultaneous validation of the hardware and our application software. The maturity of Target's retargetable C compilation technology and the automated path to hardware generation that they offer were compelling reasons to select the Chess/Checkers tool-suite."
Don Shaver
Gennum Corporation
Burlington, Canada
Read all testimonies
Imec and Target Present Multi-Standard Low-Power LDPC Engine for Multi-Gbps Wireless Communication
Huawei Adopts Target’s IP Designer Tool-Suite to Build Next-Generation Baseband DSP
Target’s IP Designer Tool-Suite Adopted by Dialog Semiconductor to Create OpenVG Graphics Processor Core
- IP Designer
- A retargetable tool-suite
for ASIP design
- IP Programmer
- Efficient SDKs for
ASIP-based SoCs
- ASIP Modeling Services
- Support services to develop nML processor models for IP Designer and IP Programmer
- MP Designer
- Multicore parallelization and platform generation
- Mobile World Congress
Barcelona, Feb. 25-28
- Embedded World
Nuremberg, Feb. 26-28
- CDNLive Silicon Valley
Santa Clara, Mar. 12
- Design Automation & Test in Europe
Grenoble, Mar. 19-21
- SNUG Silicon Valley
Santa Clara, Mar. 26
- Linley Mobile Conf.
Santa Clara, Apr. 17-18
- Design West
San Jose, Apr. 23-25
- ChipEx
Tel Aviv, May 1
- Embedded Systems Expo
Tokyo, May 8-10
- Multicore DevCon
Santa Clara, May 21-22
- Design Automation Conf.
Austin, June 3-5
We are looking for enthusiastic engineers to expand our teams in Leuven, Belgium, and Boulder, Colorado. Check out our career pages for details.
