Testimonies

NXP

"We were very impressed that for our general purpose DSP architecture, Chess was able to exploit the full 8 levels of instruction level parallelism (ILP) for many loop inner kernels. Our first application running on the Coolflow DSP prototype board is MP3 audio decoding. We are running a full featured MP3 decoder in under 15 MIPS on Coolflow, with a power consumption of less than 1 mW for typical MP3 source material."

Johan David
NXP Semiconductors
Leuven, Belgium

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News

Target Compiler Technologies Unveils MP Designer™, a New Tool-Suite for Multicore SoC Design

Conexant Adopts Target’s IP Designer Tool-Suite to Build Next-Generation Foundation DSP IP

CogniVue Adopts Target’s IP Designer Tool-Suite to Build Next-Generation Image Cognition Processor

Imec and Target Present Innovative Flexible Forward Error-Correction Solution for Software-Defined Radios

Products/Technology

IP Designer
A retargetable tool-suite
for ASIP design
IP Programmer
Efficient SDKs for
ASIP-based SoCs
ASIP Modeling Services
Support services to develop nML processor models for IP Designer and IP Programmer

SPRING 2012 EVENTS

 

  • DATE
    Dresden, Mar. 13-15
  • Synopsys SNUG
    Santa Clara, Mar. 26
  • Multicore Dev Con
    San Jose, Mar. 27-29
  • ChipEx
    Tel Aviv, May 2