Target Compiler Technologies : Testimonies

Customer testimonies

Shohei Okamura Olympus Digital System Design Corp. Tokyo, Japan Press release January 24, 2008	We consider ASIPs as an ideal solution to meet the performance, power, and flexibility requirements of our next-generation chips. We had an important need for efficient EDA tools to design such ASIPs fast and reliably. We knew of Target’s track record in this segment of the EDA market, so it was a logical choice to engage with them.

We have especially been impressed with Target’s optimising C compiler technology for ASIPs. Target’s C compiler can efficiently exploit the vector processing capabilities, the instruction-level parallelism, and the special addressing modes of our ASIP architectures. This makes it easy to program multiple algorithmic standards on our ASIPs using a high-level language like C, while obtaining an execution speed and code density comparable to manually optimised assembly code.		Takashi Hirano Olympus Digital System Design Corp. Tokyo, Japan Press release January 24, 2008

Bert Gyselinckx IMEC-NL/Holst Centre Eindhoven, The Netherlands Press release October 15, 2007	We benchmarked Target's Chess/Checkers tools and found that the resulting ASIPs have power efficiencies comparable to fixed-function hardware while still offering post-silicon programmability. Programmability is important because of the required diversity, both in terms of radio standards and system functionality. We expect that, through our collaboration with Target, we can further improve on power efficiencies for ASIP-based design as well as improve the ease of building extremely power-efficient wireless transducer systems.

With the impressive efficiency of Target's tools, we were able to build a video processing architecture that competes with hard-coded solutions while preserving programmability. The programmability enabled by Target's unique C compiler technology, in combination with their fast instruction-set simulation and on-chip debugging solution, delivers a powerful development environment and unsurpassed flexibility for product differentiation.		Dave Corbin BrightScale Sunnyvale, CA, U.S.A. Press release May 22, 2007

Benton Watson Gennum Corporation Ottawa, Canada DeepChip DAC'06 Trip Report	I've been using Target Compiler's tools to develop custom application specific cores for almost 5 years. I consider them to be a mature tool now. We have 4 custom processors in production. All the processors I've made with it have been first time right. The speed at which we can turn out a custom core using their toolset, and with only 2 engineers (one writing nML/RTL and the other verifying), still astonishes me. When writing your nML, their Chess/Checkers tool set does so many checks that if it compiles, it is generally working. The tools also point out places to optimize your nML, instruction encoding, pipelining, etc... Their tool support is the best I've ever dealt with. Even as they've reached more users, the support has not suffered. Any issues with a tool release we've ever had has been solved within a day. On all our processor projects, we've taken someone new to Target, ramped them up on Chess/Checkers and released a first version of the processor running on an FPGA in less than 6 months. The processor development has not been the critical path on any of the ASICs that were released. I believe that this can be attributed to Target Compiler's excellent tool suite.

I've been using Target Compiler's Chess/Checkers tool set for a year and a half now. In the past I designed DSP processor cores by hand... RTL coding, and it took 5-6 designers and 18 months to have some RTL sims running. With Target's tool I designed two processor cores (one RISC type and another VLIW type) in 9 months from the day I saw nML for the first time to the tapeout. Target's support was and still is excellent. That played important role in my success. I recommend Target Compiler's tools set as an efficient way to deliver application specific processor cores in a demanding time constrained environment.		Tom Skrzeszewski Gennum Corporation Ottawa, Canada DeepChip DAC'06 Trip Report

Benedetto Altieri Atmel Corporation Rome, Italy Press release July24, 2006	After an evaluation of different compiler solutions, we selected the Chess/Checkers technology of Target. In the first phase we used Target's nML processor description language and the retargetable tool suite to model our floating-point DSP architecture. We were able to tune the instruction-set architecture for better performance, using feedback from Target's retargetable compiler and simulator. In the second phase, a software development tool-kit for the DSP was generated, which Atmel can now deliver to its customers and partners.

Target's C compiler offers advanced optimizations like pointer disambiguation and software pipelining, which are very beneficial to exploit the instruction-level parallelism of VLIW architectures.		Pier Stanislao Paolucci Atmel Corporation Rome, Italy Press release July24, 2006

Andrea Ricciardi Atmel Corporation Rome, Italy Press release July24, 2006	Benchmark tests revealed that the execution time of the machine code generated by Target's C compiler is very close to the optimal solution for our DSP architecture. Target also delivered a solution for on-chip debugging of our DSP. It was easy to interface Target's debug hardware modules with the AMBA-AHB bus of our chip to access the DSP's memory sub-system.

Creating next generation signal processing systems for multi-media or modem applications that support multiple standards on the same architecture requires flexibility for programming as well as unprecedented parallel processing capabilities. Reconciling what seem to be so opposite characteristics is a cornerstone for the success of these processing platforms. Only Target's retargetable Chess/Checkers tool suite has got the right features to develop processors that offer programming flexibility using high-level languages like C while providing efficient capabilities to deploy instruction-level parallelism and to thoroughly debug the software execution. Surprisingly enough, as benchmarks demonstrated, these capabilities are coming without penalties in terms of power, performance or area for the resulting system.		Jean-Pierre Giacalone Texas Instruments Nice, France

René Kohlmann SiTel Semiconductor 's-Hertogenbosch, The Netherlands Press release March 6, 2006	In our first project, SiTel's existing GenDSP was described in Target's processor modelling language nML. A complete set of software development tools was available in about one month of time, and the VHDL hardware design could be completed a few weeks later. We were more than excited to find out that the processor's footprint could be reduced even more by introducing encoded instruction words and smaller register sets, while at the same time an efficient C compiler, simulator, and debugging environment became available to develop the application software. For our C code benchmarks, the C compiler produced optimised machine code with the same execution time and smaller program code size than our manually optimised implementation on the existing GenDSP.

We needed an efficient retargetable tool-suite as our basic infrastructure for designing novel multi-media accelerators. Next generation multi-media systems not only require extreme computational performance and low power consumption, but must also be able to cope with multiple standards for audio and video coding, and must be designed in a short time. The Chess/Checkers tool-suite enables the design of flexible processor cores that exactly combine those challenging requirements.		Hidetaka Takagi AOI Technology Tokyo, Japan Press release April 4, 2005

Takashi Hirano AOI Technology Tokyo, Japan Press release April 4, 2005	“We evaluated several commercially available retargetable tool-suites. We found Chess/Checkers to be the only solution that provided excellent support for digital signal processing functions. Moreover, we were pleased with the high quality of support offered by Target and by its Japanese agent Innotech.” Our next generation chip will contain a variety of processor cores, ranging from small application-specific micro-controllers up to parallel accelerators with vector processing capabilities and digital signal processing functions. We were impressed by the ability to model such a wide variety of architectures in Target's processor description language nML, and to quickly obtain efficient tool support for architecture exploration, optimised compilation and embedded software development, multi-processor simulation and debugging, and Verilog generation. The availability of a single retargetable tool-suite supporting these different cores, will be a strong asset for our new platform.”

We wanted our new DSP to outperform other solutions, not only in terms of power consumption and cost, but by offering very efficient C programmability at the same time. For audio applications, assembly programming has often been deemed mandatory to meet the ultra-low power requirements. However, the CoolFlux DSP product has shown us the key to compiler friendly low-power design, which is the use of retargetable compilation technology.		Johan Van Ginderdeuren Philips Applied Technologies Leuven, Belgium Press release July 7, 2004

Matthias Weiss Philips Semiconductors Dresden Dresden, Germany DeepChip DAC'03 Trip Report	Target's compiler offered an evaluation phase of Checkmate, by providing us a C compiler for our architecture, which we used for benchmarking against our existing solution. It was superior in both performance and code density. Thus, we decided to move ahead. In summary, we were very satisfied with Target's technology delivered. Especially, the very competent and easy going technical support allowed a seamless integration into our existing tool chain. Due to the support of adopting their C compiler to our architecture, the business relationship was straightforward and our technical involvement could be kept limited. Target is able to address the changing DSP architecture demands with their technology as well; they are from our perspective a very attractive compiler vendor also in future.

We were very impressed that for our general purpose DSP architecture, Chess was able to exploit the full 8 levels of instruction level parallelism (ILP) for many loop inner kernels. Our first application running on the Coolflow DSP prototype board is MP3 audio decoding. We are running a full featured MP3 decoder in under 15 MIPS on Coolflow, with a power consumption of less than 1 mW for typical MP3 source material.		Peter Dytrych Philips Applied Technologies Leuven, Belgium DSP Valley Newsletter no. 2, 2003

Ron Schiffelers Philips Semiconductors Nijmegen, The Netherlands Proc. ISPC'03	The tool chain for the Epics7B architecture has been developed by the company Target Compiler Technologies in Belgium and features the following tools: C-compiler, assembler/disassembler, linker, instruction set simulator. The high efficiency of the C-compiler allows for a good time to market performance of the software development. The way the instruction set simulator API interfaces to the outside world also allows to use the graphical user interface for silicon debugging. Furthermore it allows for the definition of a multi core application that can be simulated using several simulators, communicating to each other as defined by the Epics7B tile concept.

Target Compiler Technologies' software and high level System-C DSP model enables us to do pre-silicon architectural exploration and software development of our multi DSP core SoCs.		Jos van der Peet Philips Semiconductors Nijmegen, The Netherlands

Don Shaver Gennum Corporation Burlington, Canada Press release February 9, 2004	We wanted to design the best-in-class performance microprocessor and DSP cores for our specific type of application. Our aggressive schedules required us to perform simultaneous validation of the hardware and our application software. The maturity of Target's retargetable C compilation technology and the automated path to hardware generation that they offer were compelling reasons to select the Chess/Checkers tool-suite.

Once we had the base architectures of Yukon and our new DSP core described in nML, we were able to quickly perform architectural enhancements to find the best-in-class performance/power implementations. We were able to perform true concurrent verification of the hardware and the application software. A rapid path to an FPGA prototyping board supported our design-in activities. Having a complete software support infrastructure prior to having the silicon was a key enabler to our success. We were also impressed by the results of the hardware generation from the Chess/Checkers toolsuite; the resulting hardware implementation fully satisfied our ultra low power requirements. Another advantage was the ability to reuse the processor models (nML, C++ and VHDL) to speed up the development of derivative products in the future.		Dennis Mitchler Gennum Corporation Ottawa, Canada Press release February 9, 2004

Leon Cloetens ST Microelectronics Zaventem, Belgium Press release July 9, 2003	To reduce the risk involved and to accelerate the development time, we needed a more flexible, programmable ADSL solution. Target Compiler Technologies provided a solution that not only gave us this flexibility we required, but did not jeopardize the performance and die size characteristics that our customers demand. After a careful analysis of the alternatives on the market, we decided that the retargetable tool-suite by Target was the best solution to design the programmable modules in our system-on-chip ASIC.

The tool set allowed extensive use of co-simulation to perform hardware validation based on the same System C code compiled in the system model. We could correlate the results in a co-simulation of our VHDL and the Target ISS.		Laurent Dawance ST Microelectronics Zaventem, Belgium Press release July 9, 2003

Werner De Rammelaere Freescale Semiconductor Toulouse, France Proc. DATE'00 & Proc. ISSS'99	A key enabler to our solution is the use of a retargetable compiler such as Chess, which allows fast analysis of, and improvements to, a chosen ISA, followed by a fast and efficient compilation and simulation of the chosen target architecture. In summary, the Chess tool gives the designer immediate feedback, it permits DSP software, even the critical inner loops, to be written in C, and it makes new, specialized instructions readily accessible to the C code, often without having to make any changes to that C code.

Last updated: Thu Jan 24 2008

Customer testimonies