Resources

Video/Multimedia

Target

ASIPs: Programmable Accelerators for Multicore SoCs -
A High-Throughput JPEG Encoder Case Study
Steve Cox, Gert Goossens, Erik Brockmeyer
SoC Conference, Newport Beach, 2009

 

Texas Instruments

ASIP Design Methodology with Target's Chess/Checkers
Retargetable Tools
H. Maréchal
International Signal Processing Conference (GSPx),
Santa Clara, 2006

 

Target

Design of Application-Specific Instruction-Set Processors for Multi-Media, using a Retargetable Compilation Flow
W. Geurts, G. Goossens, D. Lanneer, J. Van Praet
International Signal Processing Conference (GSPx),
Santa Clara, 2005

 

 

 

 

 


News

Target Compiler Technologies Unveils MP Designer™, a New Tool-Suite for Multicore SoC Design

Conexant Adopts Target’s IP Designer Tool-Suite to Build Next-Generation Foundation DSP IP

CogniVue Adopts Target’s IP Designer Tool-Suite to Build Next-Generation Image Cognition Processor

Imec and Target Present Innovative Flexible Forward Error-Correction Solution for Software-Defined Radios

Products/Technology

IP Designer
A retargetable tool-suite
for ASIP design
IP Programmer
Efficient SDKs for
ASIP-based SoCs
ASIP Modeling Services
Support services to develop nML processor models for IP Designer and IP Programmer

SPRING 2012 EVENTS

 

  • DATE
    Dresden, Mar. 13-15
  • Synopsys SNUG
    Santa Clara, Mar. 26
  • Multicore Dev Con
    San Jose, Mar. 27-29
  • ChipEx
    Tel Aviv, May 2