Resources

Data Sheets

PDF

IP Designer/IP Programmer
Accelerating the Design and Programming of Application-Specific Processors

PDF

Chess
Retargetable C Compiler

PDF

Checkers
Retargetable Instruction-Set Simulator

Papers and Presentations

Target

Ultra-Low Power? Think Multi-ASIP SoC!
G. Goossens, J. Van Praet, D. Lanneer, W. Geurts
IP-07 Conference, Grenoble, December 2007

Target

Design of ASIPs in Multi-Processor SoCs using the Chess/Checkers Retargetable Tool Suite
Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet
International Symposium on System-on-Chip (SoC 2006),
Tampere, 2006

Target

Design of Low Power Processor Cores using a Retargetable Tool Flow
G. Goossens, D. Lanneer, P. Dytrych,
In: C. Piguet (ed.), "Low Power Electronics Design", CRC Press, 2005

Target

Processor Modeling and Code Selection for Retargetable Compilation
J. Van Praet, D. Lanneer, W. Geurts, G. Goossens
ACM Transactions on Design Automation of
Electronic Systems, Vol. 6, No. 3, 2001

Motorola

Catalyst: a DSIP Design Flow Development in Industry
W. De Rammelaere, K. Eckert, E. Hilkens, T. Lawell,
R.McGarity, P. Le Moenner, F. Steininger
International Symposium on System Synthesis, 1999

Also visit our Video/Multimedia, Wireless/Wireline, Audio, and Network Processing resources.

News

Target Announces Design Wins, New Positioning

Silicon Laboratories Adopts Target's IP Designer Tool-Suite

Products/Technology

IP Designer
A retargetable tool-suite
for ASIP design
IP Programmer
Efficient SDKs for
ASIP-based SoCs
ASIP Modeling Services
Support services to develop nML processor models for IP Designer and IP Programmer

RESOURCES

Data sheets, technical papers and presentations from Target and our customers

CAREERS

Opportunities to work with the leading provider of ASIP design automation tools