Data Sheets
IP Designer/IP Programmer
Accelerating the Design and Programming of Application-Specific Processors
Chess
Retargetable C Compiler
Checkers
Retargetable Instruction-Set Simulator
Papers and Presentations
Hardware Accelerator Performance in a Programmable Context - Methodology and Case Study
Steve Cox, Gert Goossens
5th Annual Multicore Expo, San Jose, April 2010
Ultra-Low Power? Think Multi-ASIP SoC!
Gert Goossens, Johan Van Praet, Dirk Lanneer, Werner Geurts
IP-07 Conference, Grenoble, December 2007
Design of ASIPs in Multi-Processor SoCs using the Chess/Checkers Retargetable Tool Suite
Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet
International Symposium on System-on-Chip (SoC 2006),
Tampere, 2006
Design of Low Power Processor Cores using a Retargetable Tool Flow
Gert Goossens, Dirk Lanneer, Peter Dytrych,
In: C. Piguet (ed.), "Low Power Electronics Design", CRC Press, 2005
Processor Modeling and Code Selection for Retargetable Compilation
J. Van Praet, D. Lanneer, W. Geurts, G. Goossens
ACM Transactions on Design Automation of
Electronic Systems, Vol. 6, No. 3, 2001
Catalyst: a DSIP Design Flow Development in Industry
W. De Rammelaere, K. Eckert, E. Hilkens, T. Lawell,
R.McGarity, P. Le Moenner, F. Steininger
International Symposium on System Synthesis, 1999
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