Partners
Target's IP Designer and IP Programmer tool-suites are interoperable with all industry-standard tool-flows from major EDA vendors, both at Electronic System Level (ESL) and Register-Transfer Level (RTL).
To ensure such interoperability, Target has joined the interoperability programs of several EDA vendors, including:
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In-Sync Program
- Interoperability between IP Designer's RTL generation component and Synopsys' Design Compiler logic synthesis environment.
- Interoperability between IP Designer's RTL generation component and Synopsys' VCS simulation environment.
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System Level Catalyst Program
- Interoperability between IP Designer's and IP Programmer's SystemC-wrapped instruction-set simulation component and Synopsys' Platform Architect virtual platform modelling environment.
- Interoperability between IP Designer's and IP Programmer's SystemC-wrapped instruction-set simulation component and Synopsys' Innovator virtual platform modelling environment.
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Value Added Partner Program
- Interoperability between IP Designer's and IP Programmer's SystemC-wrapped instruction-set simulation component and Mentor Graphics' Questa/ModelSim simulation environment.
- Interoperability between IP Designer's RTL generation component and Mentor Graphics' Questa/ModelSim simulation environment.
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EDANet Partner Program
- Interoperability between IP Designer's RTL generation component and ARM's standard cell IP libraries.
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