C Code Parallelization and Platform Generation for Heterogeneous Multicore Systems-on-Chip
MP Designer is a new tool-suite supporting the design of heterogeneous multicore systems-on-chip (SoCs). The tool-suite supports key design tasks such as the parallelization of sequential C code for multicore architectures and the generation of a communication fabric between multiple cores in SoC platforms.
- MP Designer is currently under beta test by selected customers. If you are a user of Target's IP Designer or IP Programmer tools, and you would like to participate in the MP Designer beta testing program, please contact firstname.lastname@example.org.
- As a first step in the commercial release schedule of MP Designer, Target already released a production version of its graphical multicore debugger.
MP Designer's patented technology supports the following features:
- Homogeneous SoC architectures with shared memory, as well as heterogeneous architectures with point-to-point communication links using distributed memory.
- User-guided parallelization of sequential C source code, for implementation on multiprocessor SoC architectures. The user identifies different tasks in the C source program, and assigns them to individual processor cores by means of source-code pragmas that do not essentially change the source code.
- Automatic global data-flow analysis of the code, to verify the feasibility of the parallelization proposed by the user.
- Automatic insertion of all required software code for communication and synchronization between tasks assigned to processors. This is based on a communication library using FIFO queues, which can be automatically refined in platform-specific software code.
- The parallelization kernel operates as a C source-to-source transformation tool. The original C source code structure is preserved as much as possible in the generated parallel code, facilitating visual analysis of the generated code by the user and efficient source-level debugging of the code in available software development kits (SDKs) for the different processors.
- Graphical feedback about parallelization choices, in the form of task graphs, enabling users to quickly evaluate alternative partitions of their C code such that an efficient load balancing between the different processor cores is achieved.
- MP Designer is currently intended for multicore architectures composed of ASIPs designed with the IP Designer toolsuite. MP Designer easily interfaces with IP Designer-generated SDKs for each of the ASIPs, in order to compile and co-simulate the generated software code.
- Optional platform generation capability, to automatically generate a SystemC based simulation model and a register-transfer level hardware model of a communication fabric between the different processor cores.
Portion of a task graph produced by MP Designer, for a digital radio receiver application. ENLARGE >>