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Target Compiler Technologies invented a novel design paradigm, to accelerate the development, programming and verification of flexible and royalty-free IP cores
in the form of application-specific processors (ASIPs).
At the heart of this approach is
IP Designer, a complete and retargetable
Electronic Design Automation (EDA) tool suite. The unique, patented technology
in IP Designer's optimising
C compiler enables full exploitation of the instruction level parallelism,
pipelining and the heterogeneous aspects of embedded processor architectures.
This results in highly optimised code, superior performance and energy
characteristics of the programmable device.
The IP Designer tool suite provides:
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High-level architectural exploration,
allowing designers to define and thoroughly optimise their ASIP's
architecture and instruction-set, to reach the best match of algorithm
and hardware resources.
- Automatic and efficient software
compilation, as well as cycle-accurate and instruction-accurate instruction-set simulation.
Designers can perform true concurrent engineering by
running critical parts of their C application code on the target processor.
Designers can easily retarget the compiler and instruction-set simulator to the changes made in the desired
ASIP architecture.
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- Fast
and automatic generation of the processor hardware, in the form
of a synthesisable register-transfer language (RTL) model.
- On chip debugging capabilities
and automatic test-program generation
for extensive verification of the ASIP core.
For each ASIP designed and
optimised with the IP Designer tool suite, an
ASIP-specific Software Development Kit (SDK) can be
generated, called IP
Programmer. This
SDK can be made available to software engineers
developing application software for the ASIP. IP
Programmer SDKs include ASIP-specific versions of the
optimising C compiler, assembler, instruction-set
simulator, and on-chip debugger.
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