Yokohama, January 24, 2008 – At the start of the Electronic Design and Solutions Fair in Yokohama today, Belgian EDA vendor Target Compiler Technologies said that its tools for the design of application-specific processors (ASIPs) are enjoying an increasingly strong adoption by the Japanese electronics industry. Target’s “IP Designer” tool suite (formerly “Chess/Checkers”) is especially being used by system-on-chip (SoC) design groups, in the context of advanced multi-media and wireless system designs.

“Our ASIP design tools were introduced in Japan more than three years ago,” commented Jeroen De Lille, Target’s Vice President of Sales and Marketing. “Since then, the adoption of our tools has been on a steady growth path. 2007 has been a good year, as several large Japanese electronic companies were added to our customer list. 2007 also marked the introduction of first end products in the Japanese market that are powered by ASIPs designed with our tools, notably in cell phones,” De Lille added.

Traditional SoC designs contain a combination of general-purpose processor cores and hardwired, fixed-function blocks. Next-generation SoCs call for more diversity in terms of system functionality and supported standards. This evolution has fuelled a trend to replace such hardwired blocks by more programmable architectures, without however giving up on computational performance and low power dissipation. Such a combination of features is obtained by using ASIPs, which are programmable blocks that support architectural specialisation and significantly more parallelism than conventional processors.

“We consider ASIPs as an ideal solution to meet the performance, power, and flexibility requirements of our next-generation chips,” said Shohei Okamura, General Manager of OLYMPUS DIGITAL SYSTEM DESIGN CORP. (ODS) “We had an important need for efficient EDA tools to design such ASIPs fast and reliably. We knew of Target’s track record in this segment of the EDA market, so it was a logical choice to engage with them,” Okamura continued.
ODS is using the IP Designer tool suite both for architectural exploration of its new ASIPs, for generating efficient low-power register-transfer level (RTL) implementations of these ASIPs, and for building complete software development kits to program the ASIPs from C source code.

“We have especially been impressed with Target’s optimising C compiler technology for ASIPs,” said Takashi Hirano, Senior Engineer at ODS. “Target’s C compiler can efficiently exploit the vector processing capabilities, the instruction-level parallelism, and the special addressing modes of our ASIP architectures. This makes it easy to program multiple algorithmic standards on our ASIPs using a high-level language like C, while obtaining an execution speed and code density comparable to manually optimised assembly code,” Hirano added.

“We are extremely pleased that ODS selected Target as its EDA partner for ASIP design in its next-generation SoCs,” said Gert Goossens, CEO of Target. “This move by such an important player in the multimedia and graphics market confirms the growing acceptance of the ASIP paradigm in SoC design, and strengthens Target’s position as a leading tool vendor in this space.”