Leuven, Belgium – February 9, 2004. Target Compiler Technologies NV announces that its Chess/Checkers retargetable tool-flow has enabled Gennum Corporation to accellerate the design of its newly developed ‘Yukon’ ultra low power microprocessor core, optimized for use in hearing instrument products. The Yukon core is the embedded controller used in an audio processing system that has already begun shipping in volume.

Following the success of the Yukon program, Gennum used the Chess/Checkers tool-suite to develop a new, highly optimized application specific DSP core as a key component of a new multi-processor open platform. The processing power of this platform will enable a wide variety of advanced adaptive algorithms for hearing instruments. The new processor is currently made available to Gennum’s customers on an FPGA prototyping board and will be in production later this year. 

Gennum began development of application specific cores in response to the need for specific power efficiency requirements for audio processing.  “We wanted to design the best-in-class performance microprocessor and DSP cores for our specific type of application. Our aggressive schedules required us to perform simultaneous validation of the hardware and our application software”, said Don Shaver, Director of Product Development at Gennum, Burlington. “The maturity of Target’s retargetable C compilation technology and the automated path to hardware generation that they offer were compelling reasons to select the Chess/Checkers tool-suite.”

Since its spin-off from the Belgian microelectronics research center IMEC, mid 1996, Target Compiler Technologies has quickly established a leading position in the supply of retargetable tool-suites for designing and programming flexible IP cores. Its flag-ship product Chess/Checkers provides an optimizing C compiler, an assembler/disassembler, a linker, an instruction-set simulator (ISS) with source-level debugging capabilities, an automatic hardware description language (HDL) generator and a test-program generator.  All tools are retargetable, based on the processor description language nML.

“Once we had the base architectures of Yukon and our new DSP core described in nML, we were able to quickly perform architectural enhancements to find the best-in-class performance/power implementations”, said Dennis Mitchler, Principal Engineer, DSP Architectures at Gennum’s Ottawa Design Centre. “We were able to perform true concurrent verification of the hardware and the application software. A rapid path to an FPGA prototyping board supported our design-in activities. Having a complete software support infrastructure prior to having the silicon was a key enabler to our success. We were also impressed by the results of the hardware generation from the Chess/Checkers toolsuite; the resulting hardware implementation fully satisfied our ultra low power requirements. Another advantage was the ability to reuse the processor models (nML, C++ and VHDL) to speed up the development of derivative products in the future.”

About Gennum Corporation

Gennum Corporation is a leading producer of silicon integrated circuits and hybrid circuits for the video, hearing instrument and data communications markets. The company has offices in Burlington and Ottawa, Canada, and subsidiaries in Japan and the United Kingdom. Gennum (TSX:GND) started operations in 1973, and its shares have been listed on the Toronto Stock Exchange since 1982.

About Target Compiler Technologies

Target Compiler Technologies NV introduces a novel design paradigm, to accelerate the development of flexible and royalty-free IP cores in the form of programmable ASICS and embedded processors.  At the heart of this approach is Chess/Checkers, a complete and retargetable computer-aided design environment, based on unique, patented technology.

In addition to the Chess/Checkers tool-suite, Target offers extensive training and support possibilities, including processor-modeling services, to help its customers to get to market in the fastest possible way.

Chess/Checkers has been applied successfully to design customized cores for diverse application domains, including GSM, 3G, VoIP, audio coding, ADSL, VDSL, wireless LAN, hearing instruments, mobile image processing and various control and interfacing applications.