Leuven, Belgium – May 18, 2000.
Target Compiler Technologies today announced the planned release of
two major extensions of its Chess/Checkers retargetable compilation environment,
which will significantly broaden the scope of the tools. A first announcement
concerns the release of “Go”, Target’s new tool for the generation of synthesisable
hardware description language (HDL) models of DSP cores. A second announcement
concerns the upcoming support for deeply pipelined DSP architectures in Chess/Checkers.
Target’s Chess/Checkers environment was introduced at the end of 1998. In
addition to the new tool Go, Chess/Checkers consists of a C compiler, a linker,
an instruction-set simulator and an assem-bler/disassembler. All tools are
retargetable, based on the nML processor description language. The environment
is primarily being used by designers of application-specific DSP cores, who
can optimise their DSP architecture in nML, using instantaneous feedback
from the retargetable tools.
HDL Generation
Target
considers the new Go tool as the missing link from its DSP design environment
to physical hardware. “Our customers prefer nML as a language for instruction-set
design, because it is concise and it offers immediate tool support and feedback,”
said Gert Goossens, General Manager of Target. “In the past, once the nML
was frozen the customer had to describe the processor a second time in VHDL
or Verilog, suited for synthesis. This was tedious and error-prone,” he added.
Go
automatically translates the nML processor description into VHDL code, which
can then be synthesised with available synthesis tools such as Synopsys’
VHDL Compiler and Design Compiler (TM). According to Johan Van Praet,
Product Development Manager at Target, Go supports several VHDL design styles.
“For example, the complete processor can be generated as a single-entity
VHDL description,” Van Praet said. “This results in a very compact and fast
simulating description, which relies on the synthesis capabilities of Design
Compiler, and allows for global optimisation of the processor hardware. Go
can also generate a more structural VHDL description of the processor that
allows to integrate existing hardware blocks in the design.”
According to Mark Genoe, Methodology Manager at Alcatel Microelectronics
(Zaventem, Belgium), the new Go tool opens interesting perspectives. “Strategies
for System-on-Chip design are based on different processor cores, with standardised
views and integrated support tools. There is a clear need for flexible DSP
cores as an additional component of such design platforms, provided they
are supported with efficient compilation and verification tools, and a reliable
route to VHDL synthesis. Chess/Checkers is an attractive technology to build
such cores and get the necessary support tools, but so far the route towards
VHDL synthesis was missing.”
Target believes that the impact of Go will be significant. “Many system design teams very well
understand the benefits of application-specific DSPs,” Goossens said. “But
often they’re less familiar with hardware design. Go allows them to take
the step.”
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Go will be released in June 2000. It will be demonstrated in Target’s booth at the 37th Design
Automation Conference this year. Target also announced that it plans to add
support for generating Verilog, in addition to VHDL.
Pipelining capabilities
With the support of deep pipelining,
Target is extending the architectural scope of its tools. Until now, Chess/Checkers
was restricted to processors with a simple pipeline structure.
“Initially
we have been focusing on time-stationary machines, with a two or three-stage
pipeline and all instructions executing in a single cycle,” said Dirk Lanneer,
Research and Development Manager of Target. “The time-stationary model resulted
in efficient processors with a simple control structure. However, many DSP
architectures are using complex functional units and high clock frequencies,”
Lanneer added. “This necessitates the use of more complex pipeline structures.”
According
to Ralph McGarity, Systems Manager at Motorola’s System-on-Chip Design Technology
Center (Austin, TX), the new pipelining capabilities offer an important added
value for Motorola teams using the Chess/Checkers tools. “We are using the
Target tool set at Motorola and are looking forward to additional flexibility
for future designs that we expect to be afforded by the pipelining enhancements,”
McGarity said.
To cope with deeply pipelined architectures,
Target has first extended the nML processor description language. “With these
extensions, nML can capture the full pipeline of each instruction, in a cycle-accurate
model,” said Lanneer. “The new version of the Chess/Checkers tools is retargetable
based on the extended nML language.
The new version of the Chess/Checkers tools, supporting deeply pipelined DSP architectures, will be released in Q3 of this year.
Corporate information
Target Compiler Technologies n.v.
is an innovation company, specialising in design technologies for embedded
software in electronic systems. Target was incorporated in 1996 as a spin-off
company of IMEC, the Belgian R&D centre for micro-electronics. Target’s
shareholders are IMEC v.z.w., IT Partners n.v. and Tetracom b.v.b.a.
Target’s customers are semiconductor and system companies with a focus on
telecommunications and consumer applications. Target’s main product, Chess/Checkers,
is based on a unique, patented technology initiated at IMEC.
Design Compiler is a trademark of Synopsys, Inc.
Contact
Gert Goossens
Target Compiler Technologies n.v.
Phone: +32-16-40 81 14
Fax: +32-16-40 53 00
E-mail: goossens@retarget.com
WWW: http://www.retarget.com
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