Press Release
Target extends Chess/Checkers tool-flow for ASIP design with automatic Verilog RTL generation and verification coverage analysis
San Diego, California, June 7, 2004 – Target Compiler Technologies announced two new product capabilities in Chess/Checkers, the tool-suite enabling accelerated design, programming and verification of flexible IP cores in the form of embedded processors and programmable ASICs (Application Specific Instruction-set Processors, or ASIPs).
In addition to the already supported automatic generation of VHDL RTL code of processor cores in the current version of the Chess/Checkers tool-suite, customers will be offered an automatic path to generate synthesizable Verilog RTL code. The Verilog capabilities are slated for Q3 of 2004.
GO, the retargetable RTL generator in the Chess/Checkers tool-suite, reads in a high level processor model in nML, the most widely used instruction-set architecture description language in the industry. GO automatically produces synthesisable RTL code for the embedded processor with a test-bench, and optionally supports the inclusion of an on-chip debugging unit, allowing to connect Target’s graphical debugging environment to the real hardware through means of, for example, a JTAG interface.
The track record of silicon tape outs at various accounts underlines the maturity and robustness of the GO HDL generation capabilities. Even for extremely power-critical applications such as hearing instruments, the GO tool has proven its value in terms of producing very efficient RTL code, comparable to hand-optimized design implementations.
The second new capability is in the area of test coverage for ASIP design.
In 2003, Target added the retargetable test program generator RISK to its Chess/Checkers tool-suite. RISK analyses the nML processor description and automatically generates assembly-level test programs with high fault coverage for the target processor. The generated test programs can be loaded and executed both in the ISS and in the generated HDL model of the processor. Automatic comparison of ISS and HDL simulation results is provided. Leading electronic companies have used the RISK tool for the verification of application-specific embedded processors.
Target now announced that the RISK tool has been extended to provide instruction level coverage metrics. Thanks to the new coverage analysis capabilities, engineers can significantly accelerate the verification process, thus obtaining a high-trust path towards the rapid design of new application-specific processors. The production release of these coverage analysis capabilities will be available by end 2004.
About Target Compiler Technologies
Target Compiler Technologies is the leading provider of retargetable software tools to accelerate the design, programming and verification of flexible processor cores, from embedded processors to programmable ASICs. Target’s Chess/Checkers tool-suite has been applied by customers worldwide to design customized cores for diverse application domains, including GSM, 3G, VoIP, audio coding, ADSL, VDSL, wireless LAN, WCDMA, hearing aids, mobile image processing and various control and interfacing applications. Target is headquartered in Leuven, Belgium, and has distribution channels in different parts of the world. Visit Target on the internet at www.retarget.com.
Contact
Tony Picard
Sales & Marketing Manager
Target Compiler Technologies NV
Haasrode Research Park
Technologielaan 11-0002
B-3001 Leuven, Belgium
Tel: +32 16 40 81 14
Fax: +32 16 40 53 00
Cell: +32 475 61 53 11
Email:
www.retarget.com
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