Target Compiler Technologies Releases New Multicore Debugger for its MP Designer Product Line
June 4, 2012. Today at the Design Automation Conference in San Francisco, Target announced the commercial release of a new graphical debugger tool for multicore system-on-chip architectures. This release marks the first phase in the commercial release schedule of Target’s new MP Designer™ product line.
For more information, read today's press release.
Target Unveils MP Designer™, a New Tool-Suite for Multicore SoC Design
June 3, 2011. Today at the Design Automation Conference in San Diego, Target announced the upcoming release of a new tool-suite supporting the design of heterogeneous multicore systems-on-chip (SoCs). The tool-suite, which is called MP Designer, supports key design tasks such as the parallelization of sequential C code for multicore architectures and the generation of a communication fabric between multiple cores in SoC platforms. A pre-production version of MP Designer will be demonstrated in Target’s booth at the Design Automation Conference. A full commercial release of the new tool suite is slated for early 2012. The first release is targeted to companies already using Target’s IP Designer™ tool-suite for ASIP design. Target is preparing for beta partner engagements now.
For more information, read today's press release.
Target Announces Multiple New Customer Engagements - Conexant, CogniVue and IMEC all adopt IP Designer Tool-Suite for Next-Generation Designs
June 3, 2011. Today at the Design Automation Conference in San Diego, Target announced multiple new customer wins for its IP Designer tool-suite for ASIP design. Conexant Systems is using the tool-suite to design DSP cores in both their audio and imaging product lines. CogniVue Corporation has adopted IP Designer for the design of its next generation image cognition processors. IMEC used the tool-suite to design a flexible forward error-correction ASIP for future cellular, connectivity and broadcasting standards.
For more information, read our press releases on Conexant, CogniVue, and IMEC.
Sound Design's Hearing Instrument Platform Wins EDN Innovation Award
May 1, 2010. On April 26, 2010, the winners of the 20th Annual EDN Innovation Awards were announced. The award in the Multiprocessing category went to Sound Design Technologies for Wolverine, its new open platform for hearing instruments. This platform uses four instances of an application-specific DSP which was designed with Target's IP Designer tool-suite.
For more information, read today's news flash.
GN ReSound Develops Wireless Protocol Stack for Next-Generation Hearing Instruments, using Target’s Optimizing C Compiler Technology
April 16, 2010. Target today announced that the wireless protocol stack of Range, GN ReSound’s new hearing instrument platform, was entirely developed using Target’s optimizing C compiler technology. The new platform, which incorporates GN ReSound’s next-generation ultra-low power digital signal processor called Coyote 4, offers vastly improved connectivity with the surrounding world. A key element is a wireless protocol stack that was developed entirely in C code and compiled onto the Coyote 4 DSP.
For more information, read today's press release.
Target signs Acetronix as its agent for Korea
March 31, 2010. Target and Acetronix, a leading South Korean supplier of semiconductor and software products, are pleased to announce that they have signed an exclusive agency agreement for the South Korean market. This agreement is the next step in the strategy of Target to establish local representations in regions with a high concentration of semiconductor design centers active in the development of advanced systems-on-chip (SoCs). Acetronix, headquartered in Seoul, will provide sales and marketing support for Target’s IP Designer and IP Programmer EDA tools.
For more information, read today's press release.
SiTel and Target partnership yields powerful VoIP DSP
March 8, 2010. SiTel Semiconductor today announced how its successful collaboration with Target led to the creation of customized audio DSPs for its SC14452 "Green VoIP Processor" chip, for Voice-over-IP communication in desktop and cordless (DECT, CAT-iq, DECT6.0, and K-DECT) phones. SC14452 is a 3-core chip, containing a microprocessor and two audio DSPs. The DSPs combine extreme energy efficiency with high processing performance, enabling industry-leading audio quality and power consumption.
The DSP architectures were designed and optimized using Target's IP Designer tool-suite. Low-power DSP hardware was created using IP Designer's register-transfer level (RTL) hardware generator. Audio and communication algorithms were mapped onto the DSPs in very short time using IP Designer's optimizing C compiler technology.
SiTel's Green VoIP Processor chip family won a 2009 Frost and Sullivan Green Excellence Award in recognition of its low power consumption, which is substantially below the ecodesign norms imposed by the European Commission. Last week, SiTel announced that D-Link's DPH150SE/C1 feature-richt VoIP desktop phones are based on the SC14452 chip.
For more information, read today's press release.
NXP Adopts IP Programmer Tool-Suite for Automotive RISC Processor
July 27, 2009. Target today announced a new design win from NXP Semiconductors. NXP engaged with Target as its supplier of software development kits for MRK III, NXP's latest 16-bit ultra-low power RISC processor for the automotive market. The announcement was made at the start of the 46th Design Automation Conference in San Francisco.
MRK III is intended for remote entry and security applications in the automotive industry, such as keyless access and immobilization. While previous-generation processors in the MRK family were typically programmed in low-level assembly code, C programmability was a key requirement for MRK III. Target's IP Programmer SDK with its optimizing C compiler will be used by MRK III software developers, both at NXP and at NXP’s customers.For more information, read today's press release.
GN ReSound Uses Target’s Optimizing C Compiler Technology for its Hearing Instrument DSP
April 20, 2009. At the DATE conference today Target announced that GN ReSound, a world leader in innovative hearing instruments, is relying on Target as its supplier of a complete software development kit (SDK) with an optimizing C compiler, for its Coyote-3 low-power digital signal processor.
GN ReSound initially used Target’s IP Designer product, to model the Coyote-3 architecture and validate the performance of Target’s C compilation and instruction-set simulation technology for its DSP. Then, a processor-specific SDK was generated from this model, using Target’s IP Programmer product. The resulting SDK is now in production use for the development and implementation of new advanced audio functions in high-end hearing instruments.
For more information, read today's press release.
Target Announces Key Design Wins, New Positioning, New Clients
June 9, 2008.Target Compiler Technologies™, the leader in tools used for designing and programming application-specific processors (ASIPs), announced several new design wins and also its new positioning as The ASIP Company™ The new positioning underscores the importance of the ASIP movement and of Target’s long-time leadership in this technology.
Gert Goossens, Target’s CEO, elaborates: “Since our founding, we have been focused on enabling SoC designers to create IP blocks— commonly known as ASIPs—that provide unprecedented combinations of both efficiency and flexibility. We believe our tools have been used to design more ASIP-based SoCs (in production) than any other tool suite out there.”
Target’s new positioning is backed by the launch of a renewed corporate website, and by a name change for its major products. Target’s tool-suite for the design of ASIP architectures, previously known as Chess/Checkers, is now called IP Designer™. Target’s product line of software development kits for new and existing ASIP architectures, previously known as Checkmate, is now called IP Programmer™. READ MORE >>
Newly announced customers include Silicon Laboratories, ETRI, Sound Design Technologies, and Sensata Technologies.
Atmel adopts Target's C compiler technology for its floating point DSP engine
January 28, 2008. Atmel Corporation published more details of the methodology used in its design of the mAgic DSP. mAgic is a floating-point very-long instruction word (VLIW) DSP that can deliver 1 GFLOPS performance at a clock frequency of only 100 MHz.
According to Atmel, it had ambitious goals: to create a DSP that was small, powerful, could be programmed exclusively with a C-based tool chain, and deliver C code performance equivalent to that of hand-optimised assembly code.
Atmel said that these goals were met thanks to the use of Target's IP Designer tool suite.
Details can be found in two DSP Design Line stories:
mAgic DSP optimization, part 1: hardware/software co-development
mAgic DSP optimization, part 2: writing C code
Target sees strong growth in Japan
January 24, 2008. At the Electronic Design and Solutions Fair (EDSF) in Yokohama today, Target said that its tools for the design of application-specific processors (ASIPs) are enjoying an increasingly strong adoption by the Japanese electronics industry. In 2007, several large Japanese electronic companies were added to Target's customer list.
Target's IP Designer tool suite is especially being used by system-on-chip design groups, in the context of advanced multi-media and wireless system designs. As an example, Target's press release issued at EDSF referred to a customer engagement by Olympus Digital System Design Corporation.
Jeroen De Lille joins management team
January 7, 2008. Target today announced that it recruited Mr. Jeroen De Lille as its new Vice President of Sales and Marketing. The expansion is driven by the increased customer base and the growing demand in the market for proven tools that speed the design, programming, and verification of custom processor cores.
Jeroen is a veteran of the computer and communications industry. He previously worked for Wang Laboratories, Dialogic Telecom, and Intel.
As a senior product marketing manager at Dialogic, he was a key contributor to the company's success in the EMEA region. At Intel, Jeroen served as Market Development Manager for EMEA, responsible for all signalling and media products of the modular communication platform division. Jeroen also is professor International Marketing at the MBA business school UBI in Brussels, Belgium.
More information is available in today's press release.
IMEC and Target collaborate on ultra-low power DSP design
October 15, 2007. IMEC and Target today announced that they entered into a collaboration agreement aiming at advancing the state-of-the-art in ultra-low power DSP and system-on-chip design. The new collaboration fits in IMEC's R&D activities on wireless autonomous transducer solutions at the Holst Centre in the Netherlands, and will be centered around Target's Chess/Checkers tool-suite for ASIP design.
Under the agreement, IMEC and Target will jointly investigate new design methodologies to push the power efficiencies of programmable architectures to the next level.
Also, IMEC and its partner residents of the wireless autonomous transducer solutions program will have access to Target's Chess/Checkers tool suite to design and program novel ultra-low power ASIP cores that will become the computational heart of new autonomous wireless sensor nodes.
More details can be found in the joint press release.
Target announces tool extensions for ultra-low power MPSoC
June 4, 2007. At the 44th DAC, Target announced several extensions of its Chess/Checkers tool suite, geared at the design of ultra-low power SoCs. Key to the innovation is multi-faceted support for parallelism as well as RTL-level optimisations.
First, new low-power RTL-level optimisations have been added to the hardware generation component of the Chess/Checkers tool-suite, delivering power dissipation metrics within a few percentage points of hand-optimised RTL designs.
Secondly, new fast instruction-accurate simulation techniques have been introduced, delivering over 100 times faster performance than conventional cycle-accurate simulators.
Finally, enhanced support for instruction predication has been added to the optimising C compiler component of the Chess/Checkers tool-suite.
For more information please consult our press release.
BrightScale adopts Target's C Compiler technology for BA1024 media processor
May 22, 2007. BrightScale Inc., a semiconductor company leading the revolution in programmable HDTV chip sets, has successfully adopted Target's C compiler technology for its new BrightScale ArrayTM "BA1024" media processor. This was jointly announced by Target and BrightScale at the Microprocessor Forum in San Jose, California, today.
BA1024 is a SIMD architecture with 1024 processing elements, supporting dual MPEG2 transport streams and simultaneous decoding of dual HD H.264, VC-1 and MPEG2 video, as well as advanced signal pre- and post-processing.
Target delivers a comprehensive software development kit for the BA1024, based on its patented graph-based optimising C compiler technology. This SDK provides BrightScale's customers with the ability to adapt their end products to evolving video processing algorithms and digital television standards.
With this announcement, Target adds efficient techniques for instruction predication to its C compiler, which are essential for both SIMD and VLIW compilation.
More details can be found in Target's and BrightScale's joint press release.
Target expands into North America and Japan
November 30, 2006. Target today announced that it has made two new important steps in its international expansion.
First, Target announced its expansion into the United States and Canada, with the appointment of Steve Cox as its Vice President of Business Development for North America. Steve is a 20 year veteran of the computing and EDA industry. He will be leading the deployment of Target's tools for custom processor design at a time when multi-processor system-on-chip design in America is hot, especially in the telecom and multimedia markets. Target's North American activities will be run out of Boulder, Colorado.
Secondly, Target announced that it signed an exclusive agency agreement for the Israeli market with ITEC, Israel's reputed EDA distributor based out of Tel Aviv. ITEC will deploy Target's processor design tools to the many Israeli semiconductor design centres, which today are at the forefront of the multi-processor system-on-chip design wave.
The expansion into North America and Israel is a key milestone for Target, as it marks exactly ten years of delivering market proven tools that speed the design, programming, and verification of custom processor cores.
For more details, please consult our press releases on the expansion into North America and Israel.
Atmet adopts Target's C compiler technology for its floating point DSP engine
July 24, 2006. Atmel Corporation successfully adopted Target's tool suite as an integrated design and programming environment for the floating-point DSP in its dual-processor platform. This platform is targeted at high-end consumer applications such as hands-free phones, robotics, acoustic diagnostics, sound processing, music synthesis, and ultra-sound scanners.
First, Atmel used Target's retargetable tool suite to model its floating-point DSP architecture and to tune its instruction-set architecture for better performance. Next, a software development tool-kit was generated for the DSP, which Atmel can now deliver to its customers and partners.
Atmel commented that the quick availability of an efficient C compiler was a compelling reason for selecting Target's tool suite. According to Atmel, benchmark tests revealed that the execution time of the machine code generated by Target's C compiler is very close to the optimal solution for its floating-point DSP architecture.
More details can be found in our press release.
SiTel Semiconductor selects Chess/Checkers to design DSPs for next-generation cordless and audio systems
March 6, 2006. SiTel Semiconductor has signed a multi-year license agreement to use Target's software tools to design and program its next-generation DSPs for cordless and audio systems.
As a leading supplier of chip sets for cordless communication, SiTel has a global share of more than 30% of the DECT cordless phone chip set market, and has won the market for cordless gamepads. SiTel's choice for Target's tools is driven by the company's direction towards flexible systems-on-a-chip with differentiating features for next-generation wireless systems, which may include e.g. VoIP telephony, home entertainment, gaming, and headset functions.
These functionalities necessitate more advanced small-footprint ultra-low power DSPs, supported by efficient C compilation and debugging tools.
Under the multi-year license agreement, Target provides both its retargetable Chess/Checkers tools to design new application-specific DSPs, as well as software development kits (SDKs) to enable SiTel's customers to program these DSPs.
For more information please read our press release.
AOI embarks on Chess/Checkers for multi-media chips
April 4, 2005. AOI Technology Inc. today announced that it has licensed Target's Chess/Checkers retargetable tool-suite for the design of flexible processor cores. Chess/Checkers is being used successfully by AOI Technology as its main development environment for its next-generation configurable LSI chips for multi-media systems.
AOI stated to have selected the Chess/Checkers tool-suite because of its excellent support for digital signal processing functions, and its ability to support a wide variety of architectures.
AOI Technology is a leading provider of high-performance and low-power multi-media ICs for various still image, video and audio codecs. AOI Technology, based in Tokyo, Japan, is the joint-venture of Olympus Corporation and ITX Corporation.
For more information please read the joint press release.
Philips
July 7, 2004. Philips has started the distribution of an advanced software development kit (SDK) for its CoolFlux DSP core. Thise SDK, called "Checkmate for CoolFlux DSP" was developed by Target and includes an optimising C compiler, assembler, instruction-set simulator and graphical debugger.
According to Philips, one of CoolFlux DSP's distinguishing features is that it has been designed for best C compiler performance. During the architectural design phase, Philips made intensive use of Target's Chess/Checkers retargetable tool-suite, in order to match the architecture to the application requirements and to ensure efficient C compiler support.
Next the "Checkmate for CoolFlux DSP" SDK has been automatically generated.
The SDK is already being used by CoolFlux DSP's lead customers, and an evaluation license is available via Philips to subscribers of Synopsys' DesignWare library.
This announcement was made today by Philips and Target at ESEC in Tokyo. For more info see the joint press release.
Synopsys and Philips
May 11, 2004. Synopsys and Philips announced that Philips' CoolFlux DSP is now distributed as a StarIP block in Synopsys' DesignWare program.
CoolFlux DSP is the first DSP core that becomes available to the 25,000 DesignWare users. The core joins the 16- and 32-bit microcontrollers from industry leaders such as IBM, Infineon, MIPS and NEC.
CoolFlux DSP is a 24-bit low-power audio DSP, designed by Philips using Target's Chess/Checkers tool-suite.
Using the retargetable tools technology, Philips' architecture design team was able to take C compilation aspects into account from day one, resulting in a core with excellent C compiler support.
Read more about the Synopsys/Philips partnership in their joint press release and in Synopys' Compiler magazine. For more information about CoolFlux DSP, visit the CoolFlux DSP website.
Chess/Checkers enables Gennum's first-pass working silicon for hearing instrumet chip
February 9, 2004. Genum Corporation has sucessfully designed first-pass working silicon for its Yukon ultra low power microprocessor core for hearing instrument products. To accelerate the design of Yukon, Gennum used Target's Chess/Checkers retargetable tool flow. Yukon is used in an audio processing system that has begun shipping in volume.
Following the success of Yukon, Gennum also developed a new application specific DSP core using the Chess/Checkers tool suite. This DSP will enable a variety of advanced adaptive algorithms for hearing instrument devices, and will be in production later this year.
For more information please consult our press release.
ST Microelectronics tapes out new ADSL chip designed using Chess/Checkers
July 9, 2003. ST Microelectronics has successfully taped out its latest ADSL customers premises (CPE) chip. Two of the critical blocks of this device were designed with Target's Chess/Checkers retargetable tool-suite.
Both blocks are involved in iterative algorithms and high-data throughput operations required to get the best performances of the ADSL physical layer with the latest ADSL standards, including ADSL2, and ADSL+.
The resulting product will be capable of reaching speeds up to 20 Mbps, doubling the speed of current ADSL standard products.
This design win was announced by Target today, during a press conference at ESEC in Tokyo. For more information please read our press release.
Philips designs ultra-low power audio DSP with Chess/Checkers
April 2003. Philips has successfully designed its latest audio DSP, named "CoolFlux DSP", using Target's Chess/Checkers tool-suite. The new design was announced by Philips in the April 2003 edition of the DSP Valley Newsletter.
Philips reported that significant architectural exploration was done on the CoolFlux DSP design, in very aggressive time scales. This allowed to optimally control the power consumption.
As a result, CoolFlux DSP is an ultra-low power audio core. Philips reported that a full featured MP3 decoder, automatically compiled with Target's C compiler, requires less than 15 MIPS on the CoolFlux DSP, with a power consumption of less than 1 mW.
For more details please consult the DSP Valley Newsletter article.
Target introduces processor verification tool-flow
December 12, 2002. Target announced the availability of new verification capabilities in the Chess/Checkers tool-suite.
First, a retargetable test program generator for flexible processor cores has been released. Secondly, Chess/Checkers now supports on-chip debugging of flexible processor cores. For more information please read our press release.
Tutorial on nML processor description language
June 6, 2002. An up-to-date tutorial on the nML processor description language is now available on the web, at nml.retarget.com.
Next to the basic concepts of the nML language, the tutorial describes recent language extensions to model complex pipeline and interlocking behaviour of contemporary processor architectures.