Target Announces Key Design Wins, New Positioning, New Clients
June 9, 2008.Target Compiler Technologies™, the leader in tools used for designing and programming application-specific processors (ASIPs), announced several new design wins and also its new positioning as The ASIP Company™ The new positioning underscores the importance of the ASIP movement and of Target’s long-time leadership in this technology.
Gert Goossens, Target’s CEO, elaborates: “Since our founding, we have been focused on enabling SoC designers to create IP blocks— commonly known as ASIPs—that provide unprecedented combinations of both efficiency and flexibility. We believe our tools have been used to design more ASIP-based SoCs (in production) than any other tool suite out there.”
Target’s new positioning is backed by the launch of a renewed corporate website, and by a name change for its major products. Target’s tool-suite for the design of ASIP architectures, previously known as Chess/Checkers, is now called IP Designer™. Target’s product line of software development kits for new and existing ASIP architectures, previously known as Checkmate, is now called IP Programmer™. READ MORE >>
Newly announced customers include Silicon Laboratories, ETRI, Sound Design Technologies, and Sensata Technologies.
Atmel adopts Target's C compiler technology for its floating point DSP engine
January 28, 2008. Atmel Corporation published more details of the methodology used in its design of the mAgic DSP. mAgic is a floating-point very-long instruction word (VLIW) DSP that can deliver 1 GFLOPS performance at a clock frequency of only 100 MHz.
According to Atmel, it had ambitious goals: to create a DSP that was small, powerful, could be programmed exclusively with a C-based tool chain, and deliver C code performance equivalent to that of hand-optimised assembly code.
Atmel said that these goals were met thanks to the use of Target's IP Designer tool suite.
Details can be found in two DSP Design Line stories:
mAgic DSP optimization, part 1: hardware/software co-development
mAgic DSP optimization, part 2: writing C code
Target sees strong growth in Japan
January 24, 2008. At the Electronic Design and Solutions Fair (EDSF) in Yokohama today, Target said that its tools for the design of application-specific processors (ASIPs) are enjoying an increasingly strong adoption by the Japanese electronics industry. In 2007, several large Japanese electronic companies were added to Target's customer list.
Target's IP Designer tool suite is especially being used by system-on-chip design groups, in the context of advanced multi-media and wireless system designs. As an example, Target's press release issued at EDSF referred to a customer engagement by Olympus Digital System Design Corporation.
Jeroen De Lille joins management team
January 7, 2008. Target today announced that it recruited Mr. Jeroen De Lille as its new Vice President of Sales and Marketing. The expansion is driven by the increased customer base and the growing demand in the market for proven tools that speed the design, programming, and verification of custom processor cores.
Jeroen is a veteran of the computer and communications industry. He previously worked for Wang Laboratories, Dialogic Telecom, and Intel.
As a senior product marketing manager at Dialogic, he was a key contributor to the company's success in the EMEA region. At Intel, Jeroen served as Market Development Manager for EMEA, responsible for all signalling and media products of the modular communication platform division. Jeroen also is professor International Marketing at the MBA business school UBI in Brussels, Belgium.
More information is available in today's press release.
IMEC and Target collaborate on ultra-low power DSP design
October 15, 2007. IMEC and Target today announced that they entered into a collaboration agreement aiming at advancing the state-of-the-art in ultra-low power DSP and system-on-chip design. The new collaboration fits in IMEC's R&D activities on wireless autonomous transducer solutions at the Holst Centre in the Netherlands, and will be centered around Target's Chess/Checkers tool-suite for ASIP design.
Under the agreement, IMEC and Target will jointly investigate new design methodologies to push the power efficiencies of programmable architectures to the next level.
Also, IMEC and its partner residents of the wireless autonomous transducer solutions program will have access to Target's Chess/Checkers tool suite to design and program novel ultra-low power ASIP cores that will become the computational heart of new autonomous wireless sensor nodes.
More details can be found in the joint press release.
Target announces tool extensions for ultra-low power MPSoC
June 4, 2007. At the 44th DAC, Target announced several extensions of its Chess/Checkers tool suite, geared at the design of ultra-low power SoCs. Key to the innovation is multi-faceted support for parallelism as well as RTL-level optimisations.
First, new low-power RTL-level optimisations have been added to the hardware generation component of the Chess/Checkers tool-suite, delivering power dissipation metrics within a few percentage points of hand-optimised RTL designs.
Secondly, new fast instruction-accurate simulation techniques have been introduced, delivering over 100 times faster performance than conventional cycle-accurate simulators.
Finally, enhanced support for instruction predication has been added to the optimising C compiler component of the Chess/Checkers tool-suite.
For more information please consult our press release.