Recent News
|
 |
January 28, 2008. Atmel Corporation published
more details of the methodology used in its design
of the mAgic DSP. mAgic is a floating-point
very-long instruction word (VLIW) DSP that can deliver 1
GFLOPS performance at a clock frequency of only 100 MHz.
According to Atmel, it had ambitious goals: to create
a DSP that was small, powerful, could be programmed
exclusively with a C-based tool chain, and deliver C
code performance equivalent to that of hand-optimised
assembly code. |
|
Atmel said that these goals were met thanks to the use
of Target's IP Designer tool suite.
Details can be found in two DSP Design Line stories:
|
|
|
|
 |
January 24, 2008. At the
Electronic Design and Solutions Fair (EDSF) in Yokohama
today, Target said that its tools for the design of
application-specific processors (ASIPs) are enjoying an
increasingly strong adoption by the Japanese electronics
industry. In 2007, several large Japanese
electronic companies were added to Target's customer
list. |
|
Target's IP Designer tool suite is especially being used
by system-on-chip design groups, in the context of
advanced multi-media and wireless system designs.
As an example, Target's
press release issued at EDSF referred to a customer
engagement by Olympus Digital System Design Corporation. |
|
|
|
 |
January 7, 2008. Target today announced
that it recruited Mr. Jeroen De Lille as its new Vice
President of Sales and Marketing. The expansion is
driven by the increased customer base and the growing
demand in the market for proven tools that speed the
design, programming, and verification of custom
processor cores.
Jeroen is a veteran of the computer
and communications industry. He previously worked
for Wang Laboratories, Dialogic Telecom, and Intel. |
|
As a senior product marketing manager at Dialogic, he
was a key contributor to the company's success in the
EMEA region. At Intel, Jeroen served as Market
Development Manager for EMEA, responsible for all
signalling and media products of the modular
communication platform division. Jeroen also is
professor International Marketing at the MBA business
school UBI in Brussels, Belgium.
More information is available in today's
press
release. |
|
|
|
 |
October 15, 2007. IMEC and Target today
announced that they entered into a collaboration
agreement aiming at advancing the state-of-the-art in
ultra-low power DSP and system-on-chip design. The new
collaboration fits in IMEC's R&D activities on wireless
autonomous transducer solutions at the Holst Centre in
the Netherlands, and will be centered around Target's
Chess/Checkers tool-suite for ASIP design.
Under the
agreement, IMEC and Target will jointly investigate new
design methodologies to push the power efficiencies of
programmable architectures to the next level. |
|
Also, IMEC and its partner residents of the wireless
autonomous transducer solutions program will have access
to Target's Chess/Checkers tool suite to design and
program novel ultra-low power ASIP cores that will
become the computational heart of new autonomous
wireless sensor nodes.
More details can be found in
the joint press release. |
|
|
|
 |
June 4, 2007.
At the 44th
DAC, Target announced several extensions of its
Chess/Checkers tool suite, geared at the design of
ultra-low power SoCs. Key to the
innovation is multi-faceted support for parallelism as
well as RTL-level optimisations. First, new low-power RTL-level
optimisations have been added to the hardware generation
component of the Chess/Checkers tool-suite, delivering
power dissipation metrics within a few percentage points
of hand-optimised RTL designs. |
|
Secondly, new fast instruction-accurate simulation
techniques have been introduced, delivering over 100
times faster performance than conventional
cycle-accurate simulators. Finally, enhanced support
for instruction predication has been added to the
optimising C compiler component of the Chess/Checkers
tool-suite.
For more information please
consult our
press release. |
|
|
|
|
Consult our news archive for older items.
|
