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Functionality
Risk is
a retargetable test-program generator, that allows to quickly generate a
large number of assembly-level test-programs for the target ASIP. These
test programs can then be executed both in the ISS and in the HDL model of
the ASIP, to check for consistency of both models. This is especially
relevant if the user introduces custom hardware modules in the design.
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Features
- Using template files, the user can influence the basic structure of the generated test programs.
- Efficient
random generator functions are available, to automatically select instruction
sub-classes and bit-patterns in the generated code. Random generators
can be biased to favour error-prone patterns.
- Users
can easily deploy selective test strategies for intensive verification of
specific processor sub-systems, with a high fault coverage.
- Easy interfacing to the ISS generated by Checkers and to
RTL simulators.
Computer platforms
Risk is available for Linux and Windows.
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