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Functionality
Go is a retargetable
register-transfer language (RT:L) generator for ASIPs.
Once an ASIP architecture has been optimised using the Chess compiler
and the Checkers ISS, Go provides a quick and efficient route to hardware
for the new ASIP.
Go automatically translates the processor's nML description into synthesisable
VHDL or Verilog code. Go supports a structural design style, using synchronous logic.
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RTL synthesis
and simulation
The generated RTL description can be synthesised efficiently with standard,
commercially available synthesis tools, for either ASIC or FPGA.
Existing hardware blocks can be integrated in the RTL design.
Go optionally generates a test-bench generation for simulation.
Go optionally generates hardware modules enabling JTAG-based
on-chip debugging of the ASIP
Computer platforms
Go is available for Linux and Windows.
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