December 08, 1997, Issue: 984 Section: News Target's tools let applications software drive synthesis -- Startup shoots for app-specific DSPs Peter Clarke Leuven, Belgium - Startup Target Compiler Technologies NV says it's within weeks of launching a set of Unix-based high-level system-design tools that represent a step up in design abstraction and turn at least one aspect of traditional digital-signal-processor-based ASIC development on its head. With the tools, designers will be able to use application software to drive the exploration of different instruction sets and architectures, rather than selecting an established core that represents the best compromise among various projected performance parameters and then writing software for that core. The tools will let designers recompile their code for a number of custom architectures and run simulations before selecting and synthesizing an application-specific DSP-like processor. Because application-specific instruction processors (ASIPs) can be developed to match a particular embedded-processing requirement precisely, they can cut IC power consumption by up to 90 percent and die area by half in such embedded applications as telecommunications and consumer electronics, according to Target, which was spun off from the Interuniversities Microelectronics Center (IMEC; Leuven) "Users want application-specific processors because the performance is much better," said Target general manager Gert Goossens. "There are examples where an ASIP design uses a factor of 10 less power. But [ASIP design] is rarely done, because there is no tool support." It is that lack of support that Target claims to have addressed with its Chess/Checkers design environment. The software has been available in beta release since June. Goossens said Motorola Semiconductor Product Sector's wireless-communications center (Toulouse, France), an early customer, is using the software to develop a new DSP core for GSM mobile-telephone handsets. That's an application, Goossens said, where "you want the efficiency of custom hardware but you still need programmability; therefore you still need a DSP." Retargetable elements The Chess/Checkers environment is comprised of three main elements: the Chess C-language compiler, the Checkers instruction-set simulator and a processor-modeling language called nML. Goossens said Chess and Checkers are retargetable, meaning they can quickly be ported to an alternative ASIP architecture. According to Target documentation, systems or processor designers will be able to perform the adaptation without the aid of Target staff. The nML language enables the retargetability. Once an nML file specifies the target processor, Chess reads the file to generate low-level code from C-language software. Similarly, Checkers uses the file to accept the low-level code and simulate its running on the target processor. "We developed the nML language to model DSP," said Goossens. "It's at a much higher level than Verilog or VHDL. It's at the level of a programmer's manual-something that could be used by assembler writers." Alternative instruction-set architectures can be described in a few days' work, and their performance can be compared by running Chess and Checkers with modules of typical or critical code. Only after optimizing the instruction-set architecture is the translation made from nML to a hardware-description language such as VHDL or Verilog. Although nML is essentially a behavioral language, Goossens said, "there is some structural information. You can specify whether multiple multipliers are supported, the memory structure, the cache type and so on." Chess, Checkers and nML support the full range of traditional arithmetic, logical and control instructions. "We haven't applied Chess/Checkers to full-blown microprocessor design so far. That's not what it was developed for, and it might be difficult to do," said Goossens. "The main limitation is that we only support time-stationary coding; that is, we assume every instruction executes in a single cycle." An architecture can still have pipelining of instruction fetches, decoding and execution. But deeper pipelines or execution over multiple cycles-as are often found in RISC microprocessors-are not supported. "Single-cycle execution is a valid assumption when you are creating your own architecture," Goossens said. He said Target chose to craft Chess, the retargetable compiler, for the C language because"C is the de facto standard." The startup has no plans to address more object-oriented programming languages, such as C++ or Java, though it does "allow some features from C++ to be supported. For example, we allow user-specified data types; it's not just 32-bit data types" that are supported. To demonstrate the utility of the C compiler, Target has applied it to the Analog Devices AD2100 16-bit fixed-point DSP. Users thus have a point of reference against which to benchmark their own instruction sets and architectures, Goossens said. HDL generator To complement Chess and Checkers, Target is developing a tool that would automatically translate nML code into synthesizable VHDL. That product is slated for introduction by the end of 1998. "The first version of the HDL generator will be VHDL. We are collaborating with a local company, Easics, on the development of that," Goossens said. "Verilog will be important, and we should be able to structure it so that a Verilog version will be available only a few months later." There are also plans to develop additional analysis and diagnostic tools to sit alongside the basic Chess/Checkers design flow. "The nML language is a formal way to explore ideas," Goossens said. "The idea is to stay at the nML level until late in the design." He cited the importance of such elements as early and accurate power estimation, statistical information about the utilization of the architecture, and diagnostic information on speed and code density. Links to third-party tools "are necessary," Goossens said. "Checkers should be able to work in a cosimulation mode." Indeed, Target has already provided links so that Checkers can work with the Eagle-i simulator, from Viewlogic/Synopsys. "Our part of the cooperation has been done," Goossens said. Some extensions are still being worked on at the other end to allow Eagle-i to work with DSP simulators. Target is just over a year old and has a staff of only five. Nonetheless, Chess and Checkers come to market with a pedigree: The tools were developed by Goossens and colleagues at IMEC, Europe's leading independent research organization for silicon process technology and EDA-tool development. Goossens, Werner Guerts, Johan Van Praet and Dirk Lanneer, the four founders of Target, all transferred from IMEC with the technology. Over the past decade, IMEC has pioneered a number of high-level design tools that have been offered to industry. DSP-synthesis tools DSPstation and Mistral, for example, were transferred to Silvar-Lisco and then to what became the European Development Center of Mentor Graphics before being passed to their current owner, Frontier Design NV (Leuven) Other tools developed at IMEC include hardware/software-codesign offerings commercialized by CoWare NV. Copyright (c) 1997 CMP Media Inc.