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IP Designer
is a retargetable tool suite. Designers can define their ASIP
architecture in the nML language. Automatically
the IP Designer tools will work
for this newly specified ASIP.
nML
is the first commercially available high-level definition language, that
quickly evolved to become the de-facto standard to describe a processor architecture
and instruction set (ISA). nML
offers designers the abstraction level of a programmer's manual of a processor.
IP Designer
consists of the following retargetable tools:
- Chess is
a software compiler that maps C application programs into highly optimised
machine code for the target ASIP. Chess
can cope well with architectural peculiarities of DSP cores. Chess supports
instruction-level and data-level parallelism, deeply pipelined instructions,
specialised arithmetic functions, custom data-types, specialised address
generation units, heterogeneous register structures, and various degrees
of instruction encoding (ranging from VLIW to highly encoded instruction
sets). Chess produces machine
code in the Elf/Dwarf object file format.
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Darts
is an assembler and disassembler that translates machine code
from assembly into binary format and back.
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Checkers
is an instruction-set simulator (ISS) and graphical debugger generator. The ISS
offers bit-accurate execution
of machine code, both at cycle-accurate and instruction-accurate level. Through
a co-simulation interface, the ISS can easily be coupled
to other simulators (e.g. co-simulation with an RTL
model or with other ISSs, or integration in a SystemC or
virtual platform model). Checkers supports C source-level
debugging based on Elf/Dwarf executable files. Checkers' graphical debugger
can also connect to the processor hardware to support on-chip debugging.
Checkers produces execution profiles to drive the
optimisation of the ASIP architecture and of the
application software.
- Go
is an RTL generator that translates the nML processor description into synthesisable
register transfer language (RTL) hardware modell. A JTAG interface and a debug
controller can optionally be generated, to support on-chip
debugging.
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