Target Compiler Technologies : Products

Background Info

Application-Specific Processors (ASIPs)

Today, developers of electronic systems face the challenge of designing differentiating products with a higher level of flexibility, to be able to quickly adapt to tiered and changing market needs.

This trend to increase the flexibility of electronic devices and systems has fueled the use of IP cores in the form of application-specific processors (ASIPs), enabling both software programmability and the high performance and lower power of specialised solutions.

ASIPs span the wide architectural spectrum between general-purpose microprocessors and hardwired data paths. ASIPs can offer more instruction-level and data-level parallelism, as well as more architectural specialisation, than general-purpose solutions.

Thanks to the architectural exploration capabilities of the IP Designer retargetable tool suite, based on the nML processor description language, designers can determine the optimal operation point in the spectrum of architectural solutions for their application.

Target's customers own any ASIP core that they design with the IP Designer tool suite. As ASIPs always embed the customer's application knowledge, Target believes that a royalty free electronic design automation (EDA) business model is right for ASIPs.

Retargetable compilation

At the heart of this approach is IP Designer, a complete and retargetable Electronic Design Automation (EDA) tool suite. The unique, patented technology in IP Designer's optimising C compiler enables full exploitation of the instruction level parallelism, pipelining and the heterogeneous aspects of embedded processor architectures. This results in highly optimised code, superior performance and energy characteristics of the programmable device.

The IP Designer environment provides:

High-level architectural exploration, allowing designers to define and thoroughly optimise their ASIP's architecture and instruction-set, to reach the best match of algorithm and hardware resources.

Automatic and efficient software compilation, as well as cycle-accurate and instruction-accurate instruction-set simulation. Designers can perform true concurrent engineering by running critical parts of their C application code on the target processor. Designers can easily retarget the compiler and instruction-set simulator to the changes made in the desired ASIP architecture.

Fast and automatic generation of the processor hardware, in the form of a synthesisable register-transfer language (RTL) model.

On chip debugging capabilities and automatic test-program generation for extensive verification.

For each ASIP designed and optimised with the IP Designer tool suite, an ASIP-specific Software Development Kit (SDK) can be generated, called IP Programmer. This SDK can be made available to software engineers developing application software for the ASIP. IP Programmer SDKs include ASIP-specific versions of the optimising C compiler, assembler, instruction-set simulator, and on-chip debugger.

In addition to the IP Designer tool-suite, Target offers extensive training and support possibilities, including processor-modeling services, to help its customers to get to market in the fastest possible way.